1. Field of the Invention
The present invention relates to semiconductor storage devices, and more particularly to semiconductor storage devices in which test time for testing operation thereof can be reduced.
2. Description of the Background Art
FIG. 4 is a block diagram showing a circuit configuration of a common CMOS type static random access memory. Referring to FIG. 4, a CMOS type static random access memory (hereinafter referred to as "SRAM") includes a memory cell array 1 having memory cells two-dimensionally arranged in row and column directions, an X decoder 31 for selecting cells in memory cell array 1 in the row direction, and a Y decoder 32 for transmitting a signal selecting cells in memory cell array 1 in the column direction to a multiplexer 3. The data of a memory cell transmitted through multiplexer 3 is sensed and amplified by a sense amplifier 4. The data amplified by sense amplifier 4 is transmitted through an output buffer circuit 10 out of SRAM 30. Multiplexer 3 also has writing circuits 12 for transmitting written data to memory cells. Data is transmitted to writing circuit 12 from a data input buffer 15. Both of output buffer circuit 10 and data input buffer 15 are connected to a data input/output pin 16, through which data is transmitted into/out of the chip.
Input signals of X decoder 31 and Y decoder 32 are made by an X address buffer 43 and a Y address buffer 44, respectively. The data to X address buffer 43 and Y address buffer 44 are supplied as inputs through an X address input pin 45 and a Y address input pin 46. SRAM 30 further includes a chip selector input pin 17 for inputting a signal switching the chip operation state of SRAM 30 to either of selection/non-selection, reading/writing control input pin 18 to which a signal controlling reading/writing states of the chip is inputted, and a reading/writing control circuit 19 receiving a chip selector input signal and a reading/writing control input signal for control inside the chip.
In FIG. 4, a SRAM 30 having 4-bit configuration simultaneously processing 4 data is shown. Accordingly, memory cell array 1 is divided into four sub-arrays, which are named as I/01, I/02, I/03, I/04, respectively. Four sets of sense amplifiers 4, writing circuits 12, output buffers 10, data input buffers 15 and data output pins 16 are provided, respectively, each of which corresponds to each of four sub-arrays described-above.
Next, operation of a conventional SRAM 30 will be described. An X address input signal is supplied as an input to an X address buffer 43 through an X address input pin 45, and its output signal is decoded by an X decoder 31 to select a single row in memory cell array 1. In the same way, a Y address input signal is supplied to a Y address buffer 44 through a Y address input pin 46. Its output signal is decoded by a Y decoder 32 and a single column in each sub-array is selected by multiplexer 3.
When a chip select input signal is supplied through a chip select input pin 17 to set the chip in a selected mode, reading/writing operations from/into SRAM 30 are enabled. When a signal is inputted through a reading/writing control input pin 18 to select a reading mode, sense amplifier 4 and data input/output buffer 10 are activated by a reading/writing control circuit 19. The writing circuit 12 and data input buffer 15 are inactivated. The data of a memory cell on a column selected by Y decoder 32 among memory cells on a row selected by X decoder 31 is transmitted to sense amplifier 4 through multiplexer 3, and is amplified by sense amplifier 4. The data is transmitted to output buffer 10, and supplied as an output by the output buffer 10 to a data input/output pin 16 of SRAM 30.
On the other hand, a writing mode signal is inputted through reading/writing control input pin 18, then sense amplifiers 4 and data input/output buffers 10 are inactivated by reading/writing circuit 19. Writing circuits 12 and data input buffers 15 are activated. Similarly to the reading mode, the data of data input/output pin 16 is transmitted to a selected memory cell through data input buffer 15 and writing circuit 12, and is written into the memory cell.
When a non-selection mode signal is supplied to a chip select input pin 17, regardless of a state of the reading/writing control input pin 18, all of sense amplifiers 4, writing circuits 12, data output buffers 10 and data input buffers 15 are inactivated. Accordingly, both of the reading and writing operations are forbidden.
Next, the circuit configuration around the memory cells will be described in detail. FIG. 5 is a diagram showing a circuit configuration in a single sub-array of a typical SRAM, which corresponds to the portion designated by V of FIG. 4. The X decoder 31 is configured with a plurality of AND gates having a plurality of inputs. Multiplexer 3 includes a plurality of N channel MOSFET. A memory cell 20 is connected to an output signal line of X decoder 31, or a row selecting line (a word line) 22, and a bit line pair 21. In memory cell array 1, a bit line clamping circuit (bit line load) 23 is provided for clamping the potential of bit line 21 at a given potential.
An X address input signal is finally decoded by X decoder 31, one of a number of word lines 22 is selected, and memory cells 20 are connected to bit lines 21. A Y address input signal is finally decoded by Y decoder 32, and one pair among bit line pairs 21 is connected to sense amplifier 4 and writing circuit 12 by multiplexer 3. As a result, the data is read or written from/into a single memory cell 20 specified with the X address input signal and the Y address input signal.
A test for seeing if defect/nondefect is required for such a SRAM 30 as shown in FIGS. 4 and 5. In this test, since the SRAM shown in the figures has four data input/output pins 16, 4 bits of memory cells can be simultaneously tested.
The details of such operations of a SRAM are described in U.S. Pat. Nos. 4,542,486 and 4,161,040, for example.
In a certain test method, four pieces of identical data are written into the 4 bits of memory cells and read out. Since the data of four memory cells simultaneously tested are identical, a test can be made by checking to see if identical data are read out as outputs of four sense amplifiers 4 without individually examining data appearing at data input/output pins 16 of the chip by reading operation. Such a test method is described in U.S. Pat. Nos. 4,464,750 and 4,654,849, and Japanese Patent Publication Nos. 57-179997 and 61-51700, for example.
FIG. 6 shows conditions in the case of memory cell array 1 divided into a plurality of blocks when a SRAM has a large capacity. In the figure, (1) corresponds to the memory cell array 1 shown in FIG. 4, and (2) shows an example which is divided into two. Since the memory capacity (the number of memory cells) is the same with respect to both cases of (1) and (2), the length of word line 22 is 1/2. Since a word line 22 generally has resistance, the resistance of the word line 22 is 1/2. Also, the number of memory cells 20 on a single word line 22 is 1/2, the capacity driven by word line 22 is 1/2. As a result, CR (resistance.capacity product) indicating a delay time with respect to writing/reading of memory cell 20 is 1/4, which fasten the selection speed of memory cell 20, resulting in an advantage of speed-up. The memory cell 20 of the SRAM consumes a large amount of current when selected (when the potential of word line 22 attains H). As shown in (2) of FIG. 6, by dividing memory cell array 1, the number of memory cells 20 selected at the same time can be reduced to 1/2. As a result, the consumption power of memory cell array 1 can be reduced. Accordingly, even if memory cell array 1 is divided into a number of blocks, only one word line in one block is generally selected.
FIG. 7 is a block diagram showing a portion where an output signal of a SRAM including two or more blocks 1 of a memory cell array is processed. In FIG. 7, for simplification, data input buffer 15, writing circuit 12, X address buffer 43, Y address buffer 44, Y decoder 32 and so forth are omitted.
Generally, when a memory cell array 1 is divided into a plurality of blocks, the test of memory cell array 1 is sequentially made for each block. This is because, as described-above, memory cell blocks not used are not selected in order to reduce the consumption current. That is to say, the memory cell blocks to which a test is not applied are in normal waiting conditions. The contents thereof will be specifically described next.
Referring to FIG. 7, memory cell array 1 is divided into a memory cell array block A, a memory cell array block B etc.. Sense amplifiers 4a and 4b connected to each memory cell array block A and B are connected to data output lines through transfer gates 41a and 41b, respectively, and each data output line is connected to data input/output pin 16 through an output buffer circuit 10. The data output line is connected to a data check circuit 5, and an output from the data check circuit 5 is supplied as an output out of the chip through check data output pin 24.
The case where memory cell array block A is tested will be described. Sense amplifier 4a of block A is then connected to output buffer 10 and data check circuit 5 through transfer gate 41a by a block selector BS1. After completion of the test of block A, the sense amplifier 4a of block A is separated by block selector BS1. Subsequently, sense amplifier 4b of block B is connected to data check circuit 5 and output buffer 10 through transfer gate 41b instead.
Such division of a SRAM into a plurality of blocks is described in IEEE Journal of Solid-state Circuits, Vol. SC-22, No. 5; October, 1987 "A34-ns 1Mbit CMOS SRAM Using Triple Polysilicon", for example.
Block selector signals BS1, BS2 are provided from a test mode selecting circuit (not shown).
Next, a specific testing method will be described referring to FIG. 8. FIG. 8 is a diagram schematically showing conditions for testing a test device with an LSI memory tester 35. Referring to FIG. 8, the LSI memory tester 35 includes an input signal outputting portion 36 for outputting a predetermined input signal to the test device, and an output signal determining portion 37 for making a determination as to if the test device is defective or not by comparing an output signal from the test device with the input signal. An input signal (including an address signal and a control signal) is supplied to the test device from LSI memory tester 35. A comparison is made between an expected value which is expected to be supplied as an output from the test device and an actual output signal of the test device to see if the test device is normally functioning or not. When the SRAM 30 in FIG. 7 is a test device, a determination is made as described below. The data check circuit 5 is an exclusive OR circuit. The output data from each sense amplifier 4a and 4b should originally coincide with each other, so that a determination is made by the data check circuit 5 that the SRAM is defective only when all of the data do not coincide, and L is supplied to a check data output pin 24 as a FAIL signal.
A conventional semiconductor storage device was configured as described-above. Only one data check circuit 5 was provided for a plurality of memory cell array blocks. Accordingly, it was necessary to sequentially test for each block of the memory cell array in order to see if a plurality of memory cell array blocks were defective/nondefective. The conditions will be described referring to FIG. 9. That is, if a checking time for a single memory cell array block is expressed as T.sub.0, with a memory cell array divided into 16 blocks, the test time is T =16 .times.T.sub.0 as shown in the figure. That is, there has been a problem of an increase in manufacturing cost because an increase in the capacity of a memory increases the number of blocks of a memory cell array 1, which increase the test time.